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path: root/tools/perf/scripts/python/stackcollapse.py (follow)
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2019-03-06perf script python: Remove mixed indentationTony Jones1-1/+1
2019-02-25perf script python: Add Python3 support to stackcollapse.pyTony Jones1-3/+4
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
2016-06-22perf script stackcollapse: Remove reference to the perl interpreterArnaldo Carvalho de Melo1-2/+0
2016-06-21perf script: Add stackcollapse.py scriptPaolo Bonzini1-0/+127
generated by cgit v1.2.3 (git 2.39.1) at 2026-02-03 00:03:45 +0000
value at 0x200 wrong, so the value at 0x200 can be directly read. Add support for this kind of SID controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Update module descriptionBryan O'Donoghue1-1/+1 This imx-ocotp driver encapsulates support for a subset of both i.MX6 and i.MX7 processors. Update the module description to reflect. Fixes: 711d45477931 ("nvmem: octop: Add i.MX7D support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Enable i.MX7D OTP write supportBryan O'Donoghue1-2/+0 After applying patches for both banked access and write timings we can re-enable the OTP write interface on i.MX7D processors. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Add i.MX7D timing write clock setup supportBryan O'Donoghue1-7/+36 This patch adds logic to correctly setup the write timing parameters when blowing an OTP fuse for the i.MX7S/D. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated functionBryan O'Donoghue1-20/+27 The i.MX7S/D has a different set of timing requirements, as a pre-cursor to adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated function. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Add support for banked OTP addressingBryan O'Donoghue1-4/+64 The i.MX7S/D takes the bank address in the CTRLn.ADDR field and the data value in one of the DATAx {0, 1, 2, 3} register fields. The current write routine is based on writing the CTRLn.ADDR field and writing a single DATA register only. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Pass parameters via a structBryan O'Donoghue1-10/+34 It will be useful in later patches to know the register access mode and bit-shift to apply to a given input offset. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: imx-ocotp: Restrict OTP write to IMX6 processorsBryan O'Donoghue1-0/+2 i.MX7S/D have a different scheme for addressing the OTP registers inside the OCOTP block. Currently it's possible to address the wrong OTP registers given the disparity between IMX6 and IMX7 OTP addressing. Since OTP programming is one-time destructive its important we restrict this interface ASAP. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-08nvmem: uniphier: add UniPhier eFuse driverKeiji Hayashibara3-0/+110 Add eFuse driver for Socionext UniPhier series SoC. Note that eFuse device is under soc-glue and this register implements as read only. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>