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td>Dmitry Yashin1-0/+5 BBanana Pi P2 Pro is the SBC made by Shenzhen SINOVOIP based on Rockchip RK3308. Banana Pi P2 Pro features: - Rockchip RK3308B-S - DDR3 512 MB - eMMC 8 GB - 100M lan + onboard PoE - 40 pin and 12 pin headers - AP6256 BT + WIFI - TF card slot - 2x USB 2.0 (Type-C OTG and Type-A) - Headphone jack Add devicetree binding for Banana Pi P2 Pro. Signed-off-by: Dmitry Yashin <dmt.yashin@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241030202144.629956-2-dmt.yashin@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: Add new SoC dtsi for the RK3566T variantDragan Simic3-2/+92 Add new SoC dtsi file for the RK3566T variant of the Rockchip RK3566 SoC. The difference between the RK3566T variant and the "full-fat" RK3566 variant is in fewer supported CPU and GPU OPPs on the RK3566T, and in the absence of a functional NPU, which we currently don't have to worry about. Examples of the boards based on the RK3566T include the Pine64 Quartz64 Zero SBC, [1] which is yet to be supported, the Radxa ROCK 3C, and the Radxa ZERO 3E/3W SBCs, which are both already supported. Though, Radxa doesn't mention the use of RK3566T officially, but its official SBC specifications do state that the maximum frequency for the Cortex-A55 cores on those SBCs is lower than the "full-fat" RK3566's 1.8 GHz, which makes spotting the presence of the RK3566T SoC variant rather easy. [2][3][4] An additional, helpful cue is that Radxa handles the CPU and GPU OPPs for the RK3566T variant separately in its downstream kernel source. [5] The CPU and GPU OPPs supported on the RK3566T SoC variant are taken from the vendor kernel source, [6] which uses the values of the "opp-supported-hw" OPP properties to determine which ones are supported on a particular SoC variant. The actual values of the "opp-supported-hw" properties make it rather easy to see what OPPs are supported on the RK3566T SoC variant, but that, rather unfortunately, clashes with the maximum frequencies advertised officially for the Cortex-A55 CPU cores on the above-mentioned SBCs. [1][2][3][4] The vendor kernel source indicates that the maximum frequency for the CPU cores is 1.4 GHz, while the SBC specifications state that to be 1.6 GHz. Until that discrepancy is resolved somehow, let's take the safe approach and use the lower maximum frequency for the CPU cores. Update the dts files of the currently supported RK3566T-based boards to use the new SoC dtsi for the RK3566T variant. This actually takes the CPU cores and the GPUs found on these boards out of their earlier overclocks, but it also means that the officially advertised specifications [1][2][3][4] of the highest supported frequencies for the Cortex-A55 CPU cores on these boards may actually be wrong, as already explained above. The correctness of the introduced changes was validated by decompiling and comparing all affected board dtb files before and after these changes. [1] https://wiki.pine64.org/wiki/Quartz64 [2] https://dl.radxa.com/rock3/docs/hw/3c/radxa_rock3c_product_brief.pdf [3] https://dl.radxa.com/zero3/docs/hw/3e/radxa_zero_3e_product_brief.pdf [4] https://dl.radxa.com/zero3/docs/hw/3w/radxa_zero_3w_product_brief.pdf [5] https://github.com/radxa/kernel/commit/2dfd51da472e7ebb5ef0d3db78f902454af826b8 [6] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed561650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi Cc: TL Lim <tllim@pine64.org> Cc: Marek Kraus <gamiee@pine64.org> Cc: Tom Cubie <tom@radxa.com> Cc: FUKAUMI Naoki <naoki@radxa.com> Helped-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Helped-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/a85b9bdc176c542fea261fe7ef37697aebb42e8b.1730516702.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: Prepare RK356x SoC dtsi files for per-variant OPPsDragan Simic4-116/+236 Rename the Rockchip RK356x SoC dtsi files and, consequently, adjust their contents appropriately, to prepare them for the ability to specify different CPU and GPU OPPs for each of the supported RK356x SoC variants. The first new RK356x SoC variant to be introduced is the RK3566T, which the Pine64 Quartz64 Zero SBC is officially based on. [1] Some other SBCs are also based on the RK3566T variant, including Radxa ROCK 3C and ZERO 3E/3W, but the slight trouble is that Radxa doesn't state that officially. Though, it's rather easy to spot the RK3566T on such boards, because their official specifications state that the maximum frequency for the Cortex-A55 cores is lower than the "full-fat" RK3566's 1.8 GHz. [2][3][4] These changes follow the approach used for the Rockchip RK3588 SoC variants, which was introduced and described further in commit def88eb4d836 ("arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPs"). Please see that commit for a more detailed explanation. No functional changes are introduced, which was validated by decompiling and comparing all affected board dtb files before and after these changes. In more detail, the affected dtb files have some of their blocks shuffled around a bit and some of their phandles have different values, as a result of the changes to the order in which the building blocks from the parent dtsi files are included, but they effectively remain the same as the originals. As a side note, due to the nature of introduced changes, this commit is a bit more readable when viewed using the --break-rewrites option for git-log(1). [1] https://wiki.pine64.org/wiki/Quartz64 [2] https://dl.radxa.com/rock3/docs/hw/3c/radxa_rock3c_product_brief.pdf [3] https://dl.radxa.com/zero3/docs/hw/3e/radxa_zero_3e_product_brief.pdf [4] https://dl.radxa.com/zero3/docs/hw/3w/radxa_zero_3w_product_brief.pdf Related-to: def88eb4d836 ("arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPs") Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/77e7450b8280bbdf4e2dc47366c9da85d4d8d1de.1730516702.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: Update CPU OPP voltages in RK356x SoC dtsiDragan Simic2-6/+13 Update the lower/upper voltage limits and the exact voltages for the Rockchip RK356x CPU OPPs, using the most conservative values (i.e. the highest per-OPP voltages) found in the vendor kernel source. [1] Using the most conservative per-OPP voltages ensures reliable CPU operation regardless of the actual CPU binning, with the downside of possibly using a bit more power for the CPU cores than absolutely needed. Additionally, fill in the missing "clock-latency-ns" CPU OPP properties, using the values found in the vendor kernel source. [1] [1] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed561650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi Related-to: eb665b1c06bc ("arm64: dts: rockchip: Update GPU OPP voltages in RK356x SoC dtsi") Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/f816cd24b62742dd05a1b7c6fe162bb581c9b3bf.1730516702.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: Add OPP voltage ranges to RK3399 OP1 SoC dtsiDragan Simic1-26/+26 Add support for voltage ranges to the CPU, GPU and DMC OPPs defined in the SoC dtsi for Rockchip OP1, as a variant of the Rockchip RK3399. This may be useful if there are any OP1-based boards whose associated voltage regulators are unable to deliver the exact voltages; otherwise, it causes no functional changes to the resulting OPP voltages at runtime. These changes cannot cause stability issues or any kind of damage, because it's perfectly safe to use the highest voltage from an OPP group for each OPP in the same group. The only possible negative effect of using higher voltages is wasted energy in form of some additionally generated heat. Reported-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/dbee35c002bda99e44f8533623d94f202a60da95.1730881777.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: Enable HDMI0 on Indiedroid NovaChris Morgan1-0/+50 Enable the HDMI0 port for the Indiedroid Nova. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20241031150505.967909-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: Enable GPU on Indiedroid NovaChris Morgan1-0/+5 Enable the GPU for the Indiedroid Nova. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20241031150505.967909-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: correct analog audio name on Indiedroid NovaChris Morgan1-1/+1 Correct the audio name for the Indiedroid Nova from rockchip,es8388-codec to rockchip,es8388. This name change corrects a kernel log error of "ASoC: driver name too long 'rockchip,es8388-codec' -> 'rockchip_es8388'". Fixes: 3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board") Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20241031150505.967909-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-09arm64: dts: rockchip: sort rk3588s-rock5a properly in MakefileFUKAUMI Naoki1-1/+1 sort target dtb files properly in Makefile for rockchip. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241028072344.1514-1-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 2024-11-07arm64: dts: sun50i-a64-pinephone: Add mount-matrix for PinePhone magnetometersShoji Keita1-0/+6 For lis3mdl, values are based on datasheet and PCB drawing and tested on a real device. For af8133j, values are from testing on a real device. Signed-off-by: Shoji Keita <awaittrot@shjk.jp> Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Link: https://patch.msgid.link/20240908214718.36316-3-andrej.skvortzov@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2024-11-07arm64: dts: sun50i-a64-pinephone: Add AF8133J to PinePhoneIcenowy Zheng1-0/+12 New batches of PinePhones switched the magnetometer to AF8133J from LIS3MDL because lack of ST components. Both chips use the same PB1 pin, but in different modes. LIS3MDL uses it as an gpio input to handle interrupt. AF8133J uses it as an gpio output as a reset signal. It wasn't possible at runtime to enable both device tree nodes and detect supported sensor at probe time, because both drivers try to acquire the same gpio in different modes. Device tree fixup will be done in firmware without introducing new board revision and new dts. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Link: https://patchwork.ozlabs.org/project/uboot/patch/20240211092824.395155-1-andrej.skvortzov@gmail.com/ Link: https://patch.msgid.link/20240908214718.36316-2-andrej.skvortzov@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2024-11-06riscv: dts: thead: Add TH1520 ethernet nodesEmil Renner Berthing3-0/+260 Add gmac, mdio, and phy nodes to enable the gigabit Ethernet ports on the BeagleV Ahead and Sipeed Lichee Pi 4a boards. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [drew: change apb registers from syscon to second reg of gmac node, add phy reset delay properties for beaglev ahead] Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> 2024-11-06ARM: dts: allwinner: Remove accidental suniv duplicatesCsókás, Bence1-4/+0 Allwinner suniv boards' DT files were accidentally duplicated in the Makefile when they were moved to the new directory structure. Remove these duplicates for code cleanness. Fixes: 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories") Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20241104230628.3736186-1-csokas.bence@prolan.hu Signed-off-by: Chen-Yu Tsai <wens@csie.org> 2024-11-05arm64: dts: marvell: Drop undocumented SATA phy namesRob Herring (Arm)6-9/+0 While "phy-names" is allowed for sata-port nodes, the names used aren't documented and are incorrect ("sata-phy" is what's documented). The name for a single entry is fairly useless, so just drop the property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> 2024-11-05ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity boardVarshini Rajendran2-0/+327 Add device tree file for sam9x75 curiosity board. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Reviewed-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com> Link: https://lore.kernel.org/r/20241010120444.93252-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> 2024-11-05dt-bindings: arm: add sam9x75 curiosity boardVarshini Rajendran1-0/+6 Add documentation for SAM9X75 Curiosity board. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20241010120438.93201-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>