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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-10-14 22:18:04 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-10-16 18:21:09 +0300 |
| commit | d7cc4b6bc951c52d6dfc0e3cbcc81e900100c2a6 (patch) | |
| tree | 881c838c6d66e65b04c7d45fea58949974149cf3 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 4157c75604c7adc87e1a5ae94074621bfad5a3fe (diff) | |
| download | linux-d7cc4b6bc951c52d6dfc0e3cbcc81e900100c2a6.tar.gz linux-d7cc4b6bc951c52d6dfc0e3cbcc81e900100c2a6.zip | |
drm/i915/dsc: Add prefill helper for DSC
Add intel_vdsc_prefill_lines() which tells us how many extra lines
of latency the DSC adds to the pipe prefill.
We shouldn't need a "worst case" vs, "current case" split here
as the DSC state should only change during full modesets.
The returned numbers are in .16 binary fixed point.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions