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2022-09-23Merge tag 'riscv-for-linus-6.0-rc7' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds-0/+5
2022-09-17RISC-V: Avoid coupling the T-Head CMOs and ZicbomPalmer Dabbelt-1/+5
2022-09-13RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt-0/+1
2022-09-01Merge tag 'kvm-s390-master-6.0-1' of git://git.kernel.org/pub/scm/linux/kerne...Paolo Bonzini-0/+14
2022-08-19riscv: kvm: move extern sbi_ext declarations to a headerConor Dooley-0/+12
2022-08-18riscv: traps: add missing prototypeConor Dooley-0/+2
2022-08-18riscv: signal: fix missing prototype warningConor Dooley-0/+12
2022-08-12RISC-V: KVM: Support sstc extensionAtish Patra-0/+8
2022-08-12perf: riscv_pmu{,_sbi}: Miscallenous improvement & fixesPalmer Dabbelt-2/+30
2022-08-11RISC-V: Improve SBI definitionsAtish Patra-2/+16
2022-08-11RISC-V: Move counter info definition to sbi header fileAtish Patra-0/+14
2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt-0/+6
2022-08-11RISC-V: Enable sstc extension parsing from DTAtish Patra-0/+1
2022-08-11RISC-V: Add SSTC extension CSR detailsAtish Patra-0/+5
2022-08-11riscv: ensure cpu_ops_sbi is declaredConor Dooley-0/+2
2022-08-11RISC-V: Declare cpu_ops_spinwait in <asm/cpu_ops.h>Ben Dooks-0/+1
2022-08-11arch/riscv: add Zihintpause supportDao Lu-3/+23
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt-2/+72
2022-08-06Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds-13/+52
2022-08-05Merge tag 'mm-stable-2022-08-03' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds-20/+0
2022-08-05Merge tag 'asm-generic-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds-1/+0
2022-08-04Merge tag 'pci-v5.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds-27/+4
2022-08-04Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds-16/+83
2022-08-03riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner-5/+43
2022-08-03Merge tag 'efi-next-for-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds-2/+0
2022-07-29RISC-V: KVM: Add support for Svpbmt inside Guest/VMAnup Patel-0/+17
2022-07-29RISC-V: KVM: Add G-stage ioremap() and iounmap() functionsAnup Patel-0/+5
2022-07-29RISC-V: KVM: Add extensible CSR emulation frameworkAnup Patel-0/+11
2022-07-29RISC-V: KVM: Add extensible system instruction emulation frameworkAnup Patel-0/+9
2022-07-29RISC-V: KVM: Factor-out instruction emulation into separate sourcesAnup Patel-10/+34
2022-07-29RISC-V: KVM: Make kvm_riscv_guest_timer_init a void functionNikolay Borisov-1/+1
2022-07-29RISC-V: KVM: Improve ISA extension by using a bitmapAtish Patra-5/+6
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner-1/+33
2022-07-22asm-generic: Add new pci.h and use itStafford Horne-19/+4
2022-07-22PCI: Move isa_dma_bridge_buggy out of asm/dma.hStafford Horne-2/+0
2022-07-22PCI: Remove pci_get_legacy_ide_irq() and asm-generic/pci.hStafford Horne-6/+0
2022-07-21riscv: Add macro for multiple nop instructionsPalmer Dabbelt-7/+18
2022-07-21riscv: convert the t-head pbmt errata to use the __nops macroHeiko Stuebner-7/+1
2022-07-21riscv: introduce nops and __nops macros for NOP sequencesHeiko Stuebner-0/+17
2022-07-19RISC-V: Support for 64bit hartid on RV64 platformsPalmer Dabbelt-4/+4
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L-2/+2
2022-07-19riscv: smp: Add 64bit hartid support on RV64Sunil V L-2/+2
2022-07-17riscv/mm: enable ARCH_HAS_VM_GET_PAGE_PROTAnshuman Khandual-20/+0
2022-07-11riscv: Fix missing PAGE_PFN_MASKAlexandre Ghiti-9/+9
2022-06-28efi: Simplify arch_efi_call_virt() macroSudeep Holla-2/+0
2022-06-28arch/*/: remove CONFIG_VIRT_TO_BUSArnd Bergmann-1/+0
2022-06-22RISC-V: PCI: Avoid handing out address 0 to devicesMaciej W. Rozycki-2/+2
2022-06-17riscv: Fix ALT_THEAD_PMA's asm parametersNathan Chancellor-7/+7
2022-06-16riscv: switch has_fpu() to the unified static key mechanismJisheng Zhang-2/+2
2022-06-16riscv: introduce unified static key mechanism for ISA extensionsJisheng Zhang-0/+25