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path: root/drivers/gpu
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2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak-7/+36
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak-0/+25
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak-2/+8
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak-7/+49
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak-1/+6
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak-105/+98
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak-32/+92
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak-21/+47
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak-9/+14
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak-27/+35
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola-15/+15
2025-11-19drm/msm: Switch to use %ptSpAndy Shevchenko-4/+2
2025-11-19drm/amdgpu: Switch to use %ptSpAndy Shevchenko-2/+1
2025-11-19drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian-4/+7
2025-11-18drm/xe/vf: Shadow buffer management for CCS read/write operationsSatyanarayana K V P-7/+73
2025-11-18drm/xe/sa: Shadow buffer support in the sub-allocator poolSatyanarayana K V P-4/+91
2025-11-18drm/xe/irq: Handle msix vector0 interruptVenkata Ramana Nayana-17/+1
2025-11-18drm/xe: Remove duplicate DRM_EXEC selection from KconfigShuicheng Lin-1/+0
2025-11-18drm/xe/kunit: Fix forcewake assertion in mocs testMatt Roper-1/+1
2025-11-18drm/xe: Prevent BIT() overflow when handling invalid prefetch regionShuicheng Lin-2/+4
2025-11-18drm/radeon: delete radeon_fence_process in is_signaled, no deadlockRobert McClinton-7/+0
2025-11-18drm/amd/display: Fix pbn to kbps ConversionFangzhi Zuo-36/+23
2025-11-18drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5Ivan Lipski-0/+8
2025-11-18drm/amd/display: Add an HPD filter for HDMIIvan Lipski-0/+144
2025-11-18drm/amd/display: Increase DPCD read retriesMario Limonciello (AMD)-1/+1
2025-11-18drm/msm/a8xx: Add support for Adreno X2-85 GPUAkhil P Oommen-0/+140
2025-11-18drm/msm/adreno: Do CX GBIF config before GMU startAkhil P Oommen-14/+54
2025-11-18drm/msm/a8xx: Add support for Adreno 840 GPUAkhil P Oommen-1/+174
2025-11-18drm/msm/adreno: Support AQE engineAkhil P Oommen-0/+28
2025-11-18drm/msm/adreno: Introduce A8x GPU SupportAkhil P Oommen-34/+1321
2025-11-18drm/msm/a6xx: Share dependency vote table with GMUAkhil P Oommen-0/+125
2025-11-18drm/msm/a6xx: Improve MX rail fallback in RPMH vote initAkhil P Oommen-11/+15
2025-11-18drm/msm/a8xx: Add support for A8x GMUAkhil P Oommen-34/+102
2025-11-18drm/msm/a6xx: Rebase GMU register offsetsAkhil P Oommen-203/+221
2025-11-18drm/msm/a6xx: Sync latest register definitionsAkhil P Oommen-691/+2339
2025-11-18drm/amd/display: Move sleep into each retry for retrieve_link_cap()Mario Limonciello (AMD)-4/+5
2025-11-18drm/amd/display: Prevent Gating DTBCLK before It Is Properly LatchedFangzhi Zuo-2/+4
2025-11-18drm/amd/display: Move analog check to dce110_hwseqTimur Kristóf-4/+5
2025-11-18drm/amd/display: Cleanup early return in construct_phyTimur Kristóf-6/+7
2025-11-18drm/amd/display: Cleanup uses of the analog flagTimur Kristóf-5/+12
2025-11-18drm/amd/display: Fix warning for analog stream encodersTimur Kristóf-1/+1
2025-11-18drm/radeon: delete radeon_fence_process in is_signaled, no deadlockRobert McClinton-7/+0
2025-11-18drm/amd/display: dc_hw_sequencer.c: remove kernel-doc commentsRandy Dunlap-40/+40
2025-11-18drm/amdgpu: Unregister mce notifierLijo Lazar-1/+27
2025-11-18drm/amd/display: Promote DC to 3.2.359Taimur Hassan-1/+1
2025-11-18drm/amd/display: Ignore Coverity false positiveTaimur Hassan-0/+1
2025-11-18drm/amd/display: Fix pbn to kbps ConversionFangzhi Zuo-36/+23
2025-11-18drm/amd/display: Check DCCG_AUDIO_DTO2 register mask existCharlene Liu-2/+4
2025-11-18drm/amd/display: Add null pointer check in link_dpmsCharlene Liu-1/+5
2025-11-18drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5Ivan Lipski-0/+8
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