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2025-10-29drm/rcar-du: dsi: Respect DSI mode flagsMarek Vasut-13/+20
2025-10-29drm/rcar-du: dsi: Clean up TXVMPSPHSETR DT macrosMarek Vasut-5/+6
2025-10-29drm/rcar-du: dsi: Clean up CLOCKSET1 CLKINSEL macrosMarek Vasut-3/+4
2025-10-29drm/rcar-du: dsi: Clean up VCLKSET register macrosMarek Vasut-7/+9
2025-10-29drm/rcar-du: dsi: Deduplicate mipi_dsi_pixel_format_to_bpp() usageMarek Vasut-4/+8
2025-10-29drm/rcar-du: dsi: Document PHTR TESTDOUT as bitfieldMarek Vasut-3/+4
2025-10-29drm/rcar-du: dsi: Document TXVMSETR PIXWDTH as bitfieldMarek Vasut-1/+2
2025-10-29drm/rcar-du: dsi: Fix missing parameter in RXSETR_...EN macrosMarek Vasut-2/+2
2025-10-29drm/i915: Add fallback for CDCLK selection when min_cdclk is too highNaladala Ramanaidu-1/+1
2025-10-28drm/xe: Limit number of jobs per exec queueShuicheng Lin-0/+39
2025-10-29drm/msm/dpu: Fix adjusted mode clock check for 3d mergeJessica Zhang-0/+3
2025-10-29drm/msm/dpu: Disable broken YUV on QSEED2 hardwareVladimir Lypak-2/+2
2025-10-29drm/msm/dpu: Require linear modifier for writeback framebuffersVladimir Lypak-0/+3
2025-10-29drm/msm/dpu: Fix pixel extension sub-samplingVladimir Lypak-4/+6
2025-10-29drm/msm/dpu: Disable scaling for unsupported scaler typesVladimir Lypak-1/+1
2025-10-29drm/msm/dpu: Propagate error from dpu_assign_plane_resourcesVladimir Lypak-1/+1
2025-10-29drm/msm/dpu: Fix allocation of RGB SSPPs without scalingVladimir Lypak-1/+1
2025-10-29drm/msm: dsi: fix PLL init in bonded modeNeil Armstrong-17/+2
2025-10-28drm/i915: Unify the logic in {skl,glk}_plane_has_*()Ville Syrjälä-10/+6
2025-10-28drm/i915: Extract glk_plane_has_planar()Ville Syrjälä-2/+11
2025-10-28drm/i915: Remove pointless crtc hw.enable checkVille Syrjälä-2/+1
2025-10-28drm/i915: Introduce intel_plane_min_height()Ville Syrjälä-6/+16
2025-10-28drm/i915: Start checking plane min size for the chroma planeVille Syrjälä-13/+5
2025-10-28drm/i915: Implement .min_plane_width() for PTL+Ville Syrjälä-0/+1
2025-10-28drm/i915: Drop the min plane width w/a adl+Ville Syrjälä-1/+11
2025-10-28drm/i915: Rewrite icl_min_plane_width()Ville Syrjälä-33/+10
2025-10-28drm/i915/dmc: Clear HRR EVT_CTL/HTP to zero on ADL-SVille Syrjälä-1/+54
2025-10-28drm/atomic: WARN about invalid drm_foo_get_state() usageVille Syrjälä-0/+8
2025-10-28drm/atomic: WARN about missing acquire_ctx in drm_atomic_get_private_obj_state()Ville Syrjälä-0/+2
2025-10-28drm/radeon: Remove redundant pm_runtime_mark_last_busy() callsSakari Ailus-26/+5
2025-10-28drm/amd: Remove redundant pm_runtime_mark_last_busy() callsSakari Ailus-55/+4
2025-10-28drm/amd/display: Fix incorrect return of vblank enable on unconfigured crtcIvan Lipski-3/+7
2025-10-28drm/amd/display: Add HDR workaround for a specific eDPAlex Hung-0/+1
2025-10-28drm/amdgpu: fix SPDX header on cyan_skillfish_reg_init.cAlex Deucher-1/+1
2025-10-28drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.hAlex Deucher-1/+1
2025-10-28drm/amdgpu: fix SPDX header on amd_cper.hAlex Deucher-1/+1
2025-10-28drm/amdgpu: fix SPDX headers on amdgpu_cper.c/hAlex Deucher-2/+2
2025-10-28drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on IcelandJohn Smith-1/+1
2025-10-28drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on FijiJohn Smith-1/+1
2025-10-28drm/amd/pm: fix smu table id bound check issue in smu_cmn_update_table()Yang Wang-1/+1
2025-10-28drm/amd/display: Don't program BLNDGAM_MEM_PWR_FORCE when CM low-power is dis...Matthew Schwartz-3/+0
2025-10-28drm/amd/display: pause the workload setting in dmKenneth Feng-0/+11
2025-10-28drm/radeon: Remove calls to drm_put_dev()Daniel Palmer-21/+4
2025-10-28drm/radeon: Do not kfree() devres managed rdevDaniel Palmer-1/+0
2025-10-28drm/amd: Check that VPE has reached DPM0 in idle handlerMario Limonciello-4/+30
2025-10-28drm/mediatek: Fix device use-after-free on unbindJohan Hovold-10/+0
2025-10-28drm/amdgpu/pm: Add definition for gpu_metrics v1.9Lijo Lazar-0/+117
2025-10-28drm/amdkfd: Fix Unchecked Return ValueSunday Clement-3/+6
2025-10-28drm/amdgpu: Use DC by default for BonaireTimur Kristóf-1/+0
2025-10-28drm/amd/display: Don't add freesync modes to analog displays (v2)Timur Kristóf-0/+4
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