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2025-08-15gpu: nova-core: register: move OFFSET declaration to I/O impl blockAlexandre Courbot-10/+9
2025-08-15gpu: nova-core: register: remove `try_` accessors for relative registersAlexandre Courbot-37/+1
2025-08-15gpu: nova-core: register: simplify @leaf_accessor ruleAlexandre Courbot-4/+4
2025-08-15gpu: nova-core: register: improve documentation for basic registersAlexandre Courbot-11/+13
2025-08-15gpu: nova-core: register: allow fields named `offset`Alexandre Courbot-3/+4
2025-08-15gpu: nova-core: register: add missing space in register!()Alexandre Courbot-1/+1
2025-08-15gpu: nova-core: register: minor grammar and spelling fixesJohn Hubbard-7/+7
2025-08-15Merge tag 'drm-xe-fixes-2025-08-14' of https://gitlab.freedesktop.org/drm/xe/...Dave Airlie-19/+126
2025-08-15Merge tag 'drm-intel-fixes-2025-08-13' of https://gitlab.freedesktop.org/drm/...Dave Airlie-9/+13
2025-08-14drm/panel: novatek-nt35560: Clean up driverBrigham Campbell-138/+60
2025-08-14drm: Add MIPI read_multi func and two write macrosBrigham Campbell-0/+37
2025-08-14drm/xe/pf: Set VF LMEM BAR sizeMichał Winiarski-0/+23
2025-08-14drm/mediatek: dsi: Fix DSI host and panel bridge pre-enable orderLouis-Alexis Eyraud-0/+6
2025-08-14drm/i915/display: drop __to_intel_display() usageJani Nikula-20/+5
2025-08-14drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_DJani Nikula-10/+10
2025-08-14drm/i915/gvt: convert mmio table to struct intel_displayJani Nikula-132/+134
2025-08-14drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED()Jani Nikula-4/+7
2025-08-14drm/i915/drv: pass display to HAS_DISPLAY()Jani Nikula-7/+7
2025-08-14drm/i915/switcheroo: pass display to HAS_DISPLAY()Jani Nikula-2/+4
2025-08-14drm/i915/gem: pass display to HAS_DISPLAY()Jani Nikula-1/+2
2025-08-14drm/i915/gmch: pass display to DISPLAY_VER()Jani Nikula-1/+2
2025-08-14drm/i915/dram: pass display to macros that expect displayJani Nikula-2/+3
2025-08-14drm/i915/irq: pass display to macros that expect displayJani Nikula-6/+7
2025-08-14drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register macrosJani Nikula-3/+3
2025-08-14drm/i915/clockgating: pass display to HAS_PCH_*() macrosJani Nikula-3/+9
2025-08-14drm/i915/clockgating: pass display to for_each_pipe()Jani Nikula-5/+8
2025-08-14drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER()Jani Nikula-2/+2
2025-08-14drm/i915/display: pass display to HAS_PCH_*() macrosJani Nikula-6/+3
2025-08-14drm/i915: silence rpm wakeref asserts on GEN11_GU_MISC_IIR accessJani Nikula-0/+4
2025-08-14drm/rockchip: vop2: make vp registers nonvolatilePiotr Zalewski-4/+5
2025-08-14drm/rockchip: cdn-dp: select bridge for cdp-dpRudi Heitbaum-0/+1
2025-08-14drm: renesas: rz-du: mipi_dsi: Convert to RUNTIME_PM_OPS()Geert Uytterhoeven-4/+4
2025-08-13drm/mediatek: Add error handling for old state CRTC in atomic_disableJason-JH Lin-1/+2
2025-08-14Merge tag 'amd-drm-fixes-6.17-2025-08-13' of https://gitlab.freedesktop.org/a...Dave Airlie-11/+33
2025-08-13drm/simpledrm: Use of_reserved_mem_region_to_resource() for "memory-region"Rob Herring (Arm)-10/+5
2025-08-14Merge tag 'drm-misc-next-fixes-2025-08-12' of https://gitlab.freedesktop.org/...Dave Airlie-28/+37
2025-08-13drm/msm/dpu: Initialize crtc_state to NULL in dpu_plane_virtual_atomic_check()Nathan Chancellor-1/+1
2025-08-13drm/msm: update the high bitfield of certain DSI registersAyushi Makhija-14/+14
2025-08-13drm/msm/dpu: correct dpu_plane_virtual_atomic_check()Dmitry Baryshkov-1/+1
2025-08-13drm/msm/kms: move snapshot init earlier in KMS initDmitry Baryshkov-4/+6
2025-08-13drm/msm/dsi: Fix 14nm DSI PHY PLL Lock issueLoic Poulain-42/+18
2025-08-13drm: nova: update ARef import from sync::arefShankari Anand-2/+4
2025-08-13drm/i915/wcl: Add display device infoImre Deak-1/+14
2025-08-13drm/i915/display: Add power well mapping for WCLChaitanya Kumar Borah-1/+56
2025-08-13drm/i915/tc: Debug print the pin assignment and max lane countImre Deak-4/+17
2025-08-13drm/i915/tc: Cache the pin assignment valueImre Deak-1/+3
2025-08-13dmc/i915/tc: Report pin assignment NONE in TBT-alt modeImre Deak-0/+3
2025-08-13drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpersImre Deak-10/+7
2025-08-13drm/i915/tc: Handle non-TC encoders when getting the pin assignmentImre Deak-0/+3
2025-08-13drm/i915/tc: Unify the way to get the max lane count value on MTL+Imre Deak-24/+0
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